Update November 9th: 8x4 tiles are now confirmed for the March 2027 shuttle, and the Tiny Tapeout Verilog template targets CMOS5L on its main branch. We’ve updated the rules below and added an FAQ with answers to the most common questions we’ve been getting.


Vintage oscilloscope illustration with UART, SPI, I2C, USB and 10BASE-T traces; independent time scales, not a real acquisition

Last month, we asked you to reverse engineer a chip from nothing but its layout and teased a bigger challenge. Results and our favorite writeups are coming soon. In the meantime, here’s our next challenge!

This time, you’re designing the chip, and we’ll pay to fabricate our favorite designs! We’re particularly interested in projects with unique functionality, as well as those that demonstrate novel approaches to design and verification methodologies! Winners will receive a fabricated copy of their chip, mounted on dev boards, so they can test their design in real silicon.

The challenge

Design an open-source, general-purpose protocol emulator ASIC.

Hardware protocols like UART, SPI, and I2C are simple enough that people routinely “bit-bang” them: toggle pins from software with careful timing instead of using a dedicated peripheral. A protocol emulator is a small chip built to do exactly that: a tiny CPU with an instruction set designed for reading pins, writing pins, counting cycles, and hitting timing precisely enough that you can implement a real protocol in firmware rather than in fixed logic. Something like that is a useful tool for hardware debugging and reverse engineering, which is a good part of what we do.

The hard part is flexibility. The goal isn’t to put a UART block, an SPI block, and an I2C block on one die and call it done. Your chip should be reprogrammable enough to support new protocols after fabrication, within its timing and I/O constraints. For inspiration, look at the PIO state machines on the RP2040 or the PRU cores on TI’s Sitara parts, and consider what you’d do differently.

  • Start with UART, SPI, and I2C.
  • Stretch goals include low-speed USB and 10Mbit Ethernet.
  • Other interesting protocols to consider: JTAG, SWD, PS/2, CAN bus
  • If you have access to an FPGA, consider using it to test your RTL before the ASIC flow.
  • Show us anything else your architecture makes possible that we haven’t thought of.

At Jane Street, we use Hardcaml to generate the RTL for our FPGA and ASIC designs. We are excited to see the languages and verification techniques you use, including formal methods, random constrained tests, AI-assisted verification, and more. As AI-assisted chip design becomes more common, we believe verification will be an extremely important aspect of the ASIC design flow going forwards.

The rules

  • Process: We’re targeting IHP’s 130nm CMOS5L process through our friends at Tiny Tapeout. Start with the Tiny Tapeout IHP Verilog template, which takes you from RTL to GDS. Its main branch now targets CMOS5L, so you no longer need the cmos5l branch. Set the tile size in info.yaml to 8x4.
  • Area: The maximum area is 8x4 tiles per design. This is confirmed for the March 2027 shuttle, and Tiny Tapeout says the tile sizes are final.
  • Open source: Your submission should be open source so others can use and build on it. Unlike the reverse-engineering puzzle, there’s no need to keep your work hidden until the deadline, so feel free to build in public!
  • Teams: This is a much bigger project than the puzzle, so we strongly recommend working in teams. If you’re looking for teammates or want to chat with other entrants, the Tiny Tapeout Discord has a competitions channel.
  • Deadline: Submit your design by January 18th, 2027.
  • Prize: We’ll pay to tape out the most novel designs on a Tiny Tapeout shuttle. We’re targeting the March 2027 CMOS5L shuttle, subject to the foundry schedule. Winners will receive their chip on a Tiny Tapeout demo board after fabrication, so you can test your design in silicon.

We’re aiming to announce the selected designs in early February and currently plan to tape out around four designs. After the deadline, we’ll work with winners on small non-functional fixes, like re-hardening for a newer flow.

How much fits?

An 8x4 allocation is 32 tiles. At approximately 202um × 155um per tile, that’s about 1.0 mm² of nominal tile area. As a rough estimate, budget for about 1K logic cells per tile. You may need to get creative to fit the functionality you want.

For instruction memory, SRAM can be more area-efficient than flip-flops. Tiny Tapeout has examples of SRAM running on this process node you can reference, and Ken Pettit has written a walkthrough on adding an IHP SRAM macro to a CMOS5L tile.

Run synthesis early, check the mapped cell area, and leave room for clock-tree buffers and routing. Then run the full place-and-route flow and check timing. A design that looks small enough after synthesis can still be difficult to route or too slow at your chosen clock frequency.

Getting started

If you’ve never taped out a chip before, the Tiny Tapeout documentation walks through the process end to end, and the tools are all free and open source. Start by getting a UART transmitter out of a pin. Then make it programmable.

Sign-up If you’re interested, please fill out our sign-up form. We’ll send updates about the tapeout template, deadlines, as well as providing the final submission link. Note that filling out the form is not a commitment to participating, it’s just to receive updates!

We’ll add a final submission form to this page closer to the deadline!

If you have questions along the way, check the FAQ below or reach out to asic-competition@janestreet.com.

FAQ

Entering

Who can enter, and how big can teams be?
Students and professionals are both welcome. You can enter on your own or as a team (though we recommend teams), and there’s no limit on team size. Each team submits one entry.

Did my sign-up go through?
The form doesn’t send a confirmation email. If you submitted it, you’re on the list, and there’s nothing else you need to do to register. The sign-up is just so we can send updates.

Can you review my architecture before I submit?
To keep things fair we can’t review individual designs before the deadline, but feel free to email us specific questions.

Can the board ship to my country?
Tiny Tapeout ships worldwide. If you’re unsure about your country, email us and we’ll check with them.

Design

Will I need to re-harden if the template changes?
Tiny Tapeout isn’t planning any changes to 8x4 (like pin positions, the power grid or the floorplan) that would mean re-hardening.

Can I use SRAM macros?
Yes, you can use the IHP SRAM macros, including more than one, as long as everything fits in your tiles and passes the Tiny Tapeout precheck. Ken’s walkthrough covers the RTL, LibreLane config, Metal4 power and sign-off, and uses two of them.

What pins are available?
24 digital pins: 8 inputs, 8 outputs and 8 bidirectional, plus clock and reset. There are no analog pads, but analog or mixed-signal circuits inside your design (like a PLL) are fine as long as they pass precheck.

How fast can the I/O go?
Tiny Tapeout estimates about 10 ns round trip through the pads and mux, and a max output frequency of around 66 MHz. There’s no CMOS5L silicon back yet, so these aren’t measured numbers.

What clock frequency should I target?
There’s no target. Pick one that closes timing after place-and-route and meets the protocols you want to support. The RP2350 on the demo board generates the clock, and Tiny Tapeout has confirmed 60 MHz is OK.

Can I use external parts on the board?
Yes. The chip only has digital pins (3.3V I/O on the demo board), so things like pull-ups, transceivers or level shifting go on a Pmod. Tiny Tapeout’s Pmods and recommended pinouts are good examples of what’s possible. Please document anything your design needs.

Does it have to be a CPU?
No. A CPU-style design is the most common approach, but an eFPGA, multiple engines sharing a pipeline, or something else entirely is fine, as long as the chip can be reprogrammed after fabrication to support new protocols. Whatever you build, include the software side: an assembler or toolchain (or bitstream flow) and example programs for the protocols you support.

Which protocols, and how fast?
Start with UART, SPI and I2C. Stretch goals are low-speed USB and 10 Mbit Ethernet. There are no fixed speed requirements, and standard settings (common UART baud rates, SPI modes 0-3, I2C at 100 and 400 kHz) are a good target. Running protocols concurrently, or supporting both controller and target roles, is a plus but not required. For USB and Ethernet, the more of the protocol work (line coding, CRC, clock recovery) your chip does itself, the better.

How does the program get loaded?
That’s part of your design. The microcontroller on the demo board is the natural host, but any documented host works.

What about reset?
Unlike an FPGA, flops don’t start at 0, so your design needs to use the reset signal (rst_n) to get into a known state. On the demo board it’s triggered by a button or from software. When your design is deselected it’s powered down and loses its state, so plan to reload the program after it’s selected again. Tiny Tapeout has more on moving from FPGA to ASIC.

Submission and judging

What do I submit?
A link to your public repository with your RTL, tests and a passing GDS/precheck from the Tiny Tapeout flow. Please also include documentation of your architecture and instruction set, your assembler or toolchain with example programs, and a write-up of your verification approach. A video or demo isn’t required, but we’ll look at it if you have one.

What sign-off do I need?
A clean run through the Tiny Tapeout flow and precheck. You’re not expected to run extra sign-off on top of that. We strongly recommend gate-level simulation to catch design (and occasionally tool) errors. If something slips past precheck, Tiny Tapeout will reach out and work out a fix with you.

Can I use my own GDS flow?
Please stick to the Tiny Tapeout flow, since that’s how the winning designs get onto the shuttle. If your design is big enough to hit GitHub Actions’ 6-hour limit, you can run the flow locally and submit using Tiny Tapeout’s custom GDS action instead. It still needs to pass precheck. The analog template shows how it’s set up.

Can I use my own verification tools?
Yes, use whatever tools you like, just describe them in your write-up. If some of your tests also run on open-source tools (like the cocotb tests in the template), that helps us run them ourselves, but it isn’t required.

Can I use AI tools?
Yes. Please describe how you used them in your write-up.

Does my repo need to be public now?
No. You can develop privately and make the repo public when you submit, or build in public if you prefer.

How will entries be judged?
There’s no fixed weighting. Flexibility is the main thing: can the chip be reprogrammed to support protocols it wasn’t designed for? Beyond that, we’ll look at which protocols you demonstrate, anything unique your architecture makes possible, and how you designed and verified it. A design with fewer protocols but a strong architecture and verification approach can definitely be competitive. We’ll also weigh your write-up heavily, how easy it is to read, and how clearly it explains any new techniques or flows you introduce.

Timeline and prizes

  • Submissions close January 18th, 2027.
  • We’re aiming to announce the selected designs in early February, ahead of the March 2027 CMOS5L shuttle.
  • We’re currently planning to tape out around four designs. Winners will receive their chip on the Tiny Tapeout demo board.
  • After the deadline, small non-functional fixes like re-hardening for a newer flow are fine, and we’ll work with the winners on those.

If you’re looking for teammates or want to chat with other entrants, the Tiny Tapeout Discord has a competitions channel.

Hardware at Jane Street

The hardware team at Jane Street designs FPGAs and ASICs that run some of the fastest trading systems in the world. If designing a chip for fun sounds like your kind of thing, take a look at our hardware internships and full-time roles. You can also explore Hardcaml, our open-source OCaml hardware design libraries, or stay in touch.