I am pleased to announce that we have recently released a slew of new Hardcaml libraries!
While I think the Hardcaml version now maintained at Jane Street is of higher quality than the old open-source release, it has lacked the breadth of tools that I initially supported. I think we can now claim to support a superset of the old functionality along with a much better testing story for these libraries.
In addition we have also been busy beavering away on some Hardcaml documentation. Read an introduction to the libraries, work though an example design, or fork a complete design that takes you all the way from OCaml to an FPGA bitstream.
The documentation comes in the form of MDX files which are basically executable markdown files. The nice thing about this approach is our documentation will stop compiling if we change APIs and don’t properly update it.
So, whats new?
hardcaml_circuits
provides a bunch of useful and/or interesting circuit designs. Use
them for real, or just to learn how to design and test hardware in
Hardcaml. Choose from arbiters, high-speed multiplier architectures,
sorting networks and much more!
hardcaml_xilinx_components
provides an executable that can read the Xilinx Unisims library and
generate OCaml modules for any one of thousands of basic FPGA
components. The components can be instantiated in Hardcaml circuits
in a friendly and type-safe manner.
hardcaml_xilinx
wraps up some Xilinx-specific FPGA components. A major focus is on
wrapping RAM and FIFO primitives and providing models suitable for
Hardcaml simulations. An interesting feature implements the core
Hardcaml Comb.S module type using only FPGA LUT primitives. If you
want to do some really low level design stuff on an FPGA, you should
take a look.
hardcaml_verify is
a set of verification tools, mainly centred around proving circuit
properties using SAT. And solving Sudoku of course!
hardcaml_verilator
and hardcaml_c are a
pair of high speed simulator backends with interfaces compatible with
the standard Hardcaml Cyclesim simulator. These trade compilation
time for simulation performance.
hardcaml_of_verilog
loads Verilog code into Hardcaml! Under the hood, it uses
yosys (0.9) to convert verilog to
json, then provides tools to convert that json into a Hardcaml
circuit.
hardcaml_step_testbench
is a monadic interface for driving Hardcaml simulations. It provides
a notion of a spawned task which can perform some operation in
parallel with other tasks. Everything synchronises on a clock step.
hardcaml_fixed_point
is a simple hardware fixed point datatype with all the usual
arithmetic operations. It provides a rich set of rounding and
clamping modes, and separate signed and unsigned types.
Using the libraries
All these libraries will become available in the mainline opam repository along with the v0.15 release of the Jane Street packages.
opam install hardcaml_circuits
The very latest versions are regularly released into the Jane Street bleeding edge opam repository. You can add this repository with
opam repo add janestreet-bleeding https://ocaml.janestreet.com/opam-repository
And then opam install ... the latest packages as normal.
