Advent of Code has long been a favorite December ritual at Jane Street, with many participating in the month-long puzzle challenge that encourages thoughtful engineering and out-of-the-box thinking – very much our kind of fun. Last year, Anish, a hardware engineer at Jane Street, wrote about tackling the entire series in Hardcaml, our OCaml-based hardware DSL, turning these puzzles into synthesizable FPGA circuits. If you missed it, his post, Advent of Hardcaml, walks you through how implementing such algorithms in hardware became a unique exercise in architectural design and resource optimization.

This year, we’re inviting the community to join us in that spirit with the 2025 Advent of FPGA Challenge. When the final AoC 2025 puzzle drops, pick any puzzles you like (at least one and up to as many as you want) to build synthesizable RTL with realistic I/O, bonus points if you do it in Hardcaml. We’re excited to see the clever designs created across the academic and open‑source communities, and we’d also love to get more people trying Hardcaml!

Here’s how it works:

  • Timeline: submit all solutions by January 16, 2026. (Submission Form)
  • What to submit: your code (open-sourced), testbench, and a README or document explaining your approach and how to run it.
  • Synthesizable RTL: designs should be synthesizable with realistic resource usage, but you are not required to synthesize or run it on an FPGA.
  • Original work only: no duplicates or obviously AI-generated submissions. You should be able to explain your design.
  • RTL only: any RTL language (Verilog, VHDL, Chisel, Amaranth, Filament, and similar) is welcome and Hardcaml is, of course, encouraged. High Level Synthesis languages are not supported.
  • Hardcaml resources are available here: Hardcaml tutorials

We’ll pick the three most inventive & creative contributions (as voted by the Jane Street hardware team) to receive an FPGA dev kit (the Zynq UltraScale+ Kria KV260) to try your designs at home, as well as some Jane Street swag. Anyone who successfully completes at least one puzzle in Hardcaml will also win a Jane Street Hardcaml T-shirt.

Not sure where to start? Consider exploring:

  • Scalability: can your design handle inputs 10× or even 1000× larger?
  • Efficiency: push area/performance trade-offs in the hardware.
  • Architecture: exploit FPGA-native parallelism and pipelining you can’t do on a CPU.
  • Physical synthesis: try an open-source ASIC flow (e.g., TinyTapeout).
  • Language features: showcase unique features of your favorite HDL language to generate elegant hardware beyond what you can do in Verilog/VHDL.

When you’re ready with all of the puzzle solutions you’d like to be considered, you can submit your response here. The winning solutions may be featured in a blog update!